DIGITAL INTEGRATED CIRCUITS : (Record no. 15312)

MARC details
000 -LEADER
fixed length control field 04234nam a2200349 i 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20250113133004.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 231114s2003 njuaf 001 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 0131207644
Terms of availability RM391.02
039 #9 - LEVEL OF BIBLIOGRAPHIC CONTROL AND CODING DETAIL [OBSOLETE]
Level of effort used to assign subject headings 20250113130434.0
-- 25
-- Nur Dalila binti Azhari
040 ## - CATALOGING SOURCE
Original cataloging agency ZLM
Language of cataloging eng
Transcribing agency ZLM
Modifying agency SINTU
-- UtOrBLW
-- SIRSI-AP
Description conventions rda
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Edition number 23
Classification number 621.395
090 00 - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN)
Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR) 621.395
Local cutter number (OCLC) ; Book number/undivided call number, CALL (RLIN) RAB
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Rabaey, Jan M.,
Relator term author.
9 (RLIN) 12459
245 10 - TITLE STATEMENT
Title DIGITAL INTEGRATED CIRCUITS :
Remainder of title A DESIGN PERSPECTIVE /
Statement of responsibility, etc. JAN M. RABAEY, ANANTHA CHANDRAKASAN, BORIVOJE NIKOLIC.
250 ## - EDITION STATEMENT
Edition statement SECOND EDITION
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Upper Saddle River, New Jersey :
Name of producer, publisher, distributor, manufacturer Prentice Hall/Pearson Education International,
Date of production, publication, distribution, manufacture, or copyright notice 2003.
264 #4 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Date of production, publication, distribution, manufacture, or copyright notice ©2003.
300 ## - PHYSICAL DESCRIPTION
Extent xxii, 761 pages, 4 unnumbered pages of plates :
Other physical details illustrations (some color) ;
Dimensions 24 cm.
336 ## - CONTENT TYPE
Source rdacontent
Content type term text
337 ## - MEDIA TYPE
Source rdamedia
Media type term unmediated
338 ## - CARRIER TYPE
Source rdacarrier
Carrier type term volume
490 1# - SERIES STATEMENT
Series statement Prentice Hall electronics and VLSI series
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references and index.
505 0# - FORMATTED CONTENTS NOTES
Formatted contents note (NR) (NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.) I. THE FABRICS. 1. Introduction. A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design. 2. The Manufacturing Process. The CMOS Manufacturing Process. Design Rules—The Contract between Designer and Process Engineer. Packaging Integrated Circuits. Perspective—Trends in Process Technology. 3. The Devices. The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling. 4. The Wire. A First Glance. Interconnect Parameters—Capitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future. II. A CIRCUIT PERSPECTIVE. 5. The CMOS Inverter. The Static CMOS Inverter—An Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics. 6. Designing Combinational Logic Gates in CMOS. Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era. 7. Designing Sequential Logic Circuits. Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy. III. A SYSTEM PERSPECTIVE. 8. Implementation Strategies for Digital ICS. From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. Perspective—The Implementation Platform of the Future. 9. Coping with Interconnect. Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip. 10. Timing Issues in Digital Circuits. Timing Classification of Digital Systems. Synchronous Design—An In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives. 11. Designing Arithmetic Building Blocks. Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off. 12. Designing Memory and Array Structures. The Memory Core. Memory Peripheral Circuitry. Memory Reliability and Yield. Power Dissipation in Memories. Case Studies in Memory Design. Perspective: Semiconductor Memory Trends and Evolutions. Problem Solutions. Index.<br/>
650 10 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Digital integrated circuits
General subdivision Design and construction.
9 (RLIN) 12462
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Chandrakasan, Anantha P.,
Relator term author.
9 (RLIN) 12465
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Nikolić, Borivoje,
Relator term author.
9 (RLIN) 12468
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Sodini, Charles G.,
Relator term series editor.
9 (RLIN) 12471
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Prentice Hall electronics and VLSI series
9 (RLIN) 12474
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Book
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Collection Home library Current library Shelving location Date acquired Cost, normal purchase price Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Koleksi Umum (Rak Terbuka) PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN RAK 12 15/11/2023 391.02   OS 621.395 RAB 0000006898 15/11/2023 15/11/2023 Koleksi Umum (Rak Terbuka)
    Dewey Decimal Classification     Koleksi Umum (Rak Terbuka) PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN RAK 12 15/11/2023 391.02   OS 621.395 RAB 0000006899 15/11/2023 15/11/2023 Koleksi Umum (Rak Terbuka)
    Dewey Decimal Classification     Koleksi Pinjaman Terhad (Buku bertanda Merah) PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN RAK 23 15/11/2023 391.02   RED 621.395 RAB 0000006900 15/11/2023 15/11/2023 Koleksi Pinjaman Terhad (Buku bertanda Merah)