Image from Amazon.com
Image from OpenLibrary
Chip design for submicron VLSI : CMOS layout and simulation / John P. Uyemura.
Material type:
TextPublisher: Toronto : Thomson/Nelson, 2006Publisher: ©2006Description: xvi, 411 pages : illustrations ; 25 cm + 1 CD-ROM (4 3/4 in.)Content type: - text
- unmediated
- volume
- 053446629X
- 9780534466299
- CMOS layout and simulation
- 23 621.395
| Item type | Current library | Collection | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|---|
Koleksi Pinjaman Terhad (Buku bertanda Merah)
|
PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN RAK 23 | Koleksi Pinjaman Terhad (Buku bertanda Merah) | RED 621.395 UYE (Browse shelf(Opens below)) | Available | 0000026277 | |
Koleksi Umum (Rak Terbuka)
|
PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN RAK 12 | Koleksi Umum (Rak Terbuka) | OS 621.395 UYE (Browse shelf(Opens below)) | Available | 0000026278 | |
|
Koleksi Umum (Rak Terbuka)
|
PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN RAK 12 | Koleksi Umum (Rak Terbuka) | OS 621.395 UYE (Browse shelf(Opens below)) | Available | 0000026279 | |
|
Koleksi Umum (Rak Terbuka)
|
PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN RAK 12 | Koleksi Umum (Rak Terbuka) | OS 621.395 UYE (Browse shelf(Opens below)) | Available | 0000026656 |
Browsing PERPUSTAKAAN POLITEKNIK TUANKU SYED SIRAJUDDIN shelves, Shelving location: RAK 12, Collection: Koleksi Umum (Rak Terbuka) Close shelf browser (Hides shelf browser)
|
|
|
|
|
|
|
||
| OS 621.395 ROS Reka bentuk logik / | OS 621.395 ROS Reka bentuk logik / | OS 621.395 UYE Chip design for submicron VLSI : CMOS layout and simulation / | OS 621.395 UYE Chip design for submicron VLSI : CMOS layout and simulation / | OS 621.395 UYE Chip design for submicron VLSI : CMOS layout and simulation / | OS 621.395 WAK DIGITAL DESIGN : PRINCIPLES AND PRACTICES / | OS 621.395 WAK DIGITAL DESIGN : PRINCIPLES AND PRACTICES / |
Includes bibliographical references and index
There are no comments on this title.